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MC74HC161A, MC74HC163A Presettable Counters
High-Performance Silicon-Gate CMOS
The MC74HC161A and HC163A are identical in pinout to the LS161 and LS163. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC161A and HC163A are programmable 4-bit binary counters with asynchronous and synchronous reset, respectively.
http://onsemi.com MARKING DIAGRAMS
16
16 1
* * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 192 FETs or 48 Equivalent Gates
Device Count Mode Binary Reset Mode
PDIP-16 N SUFFIX CASE 648
MC74HC16xAN AWLYYWW 1 16
16 1
SO-16 D SUFFIX CASE 751B A WL YY WW
HC16xA AWLYWW
1 = Assembly Location = Wafer Lot = Year = Work Week
I I IIIIIIIIIIII II IIIIIIIIIIII IIIIIIIIIII II II I I IIIIIIIIIIII III IIIIIIIIIIII II IIIIIIIIIIII IIIIII
HC161A HC163A Asynchronous BinaryIIIIII Synchronous
ORDERING INFORMATION
Device MC74HC16xAN MC74HC16xAD MC74HC16xADR2 14 13 12 11 Q0 Q1 Q2 Q3 RIPPLE CARRY OUT BCD OR BINARY OUTPUT Package PDIP-16 SOIC-16 SOIC-16 Shipping 2000 / Box 48 / Rail 2500 / Reel
LOGIC DIAGRAM
P0 PRESET DATA INPUTS P1 P2 P3
3 4 5 6
PIN ASSIGNMENT
RESET CLOCK P0 P1 P2 P3 ENABLE P 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RIPPLE CARRY OUT Q0 Q1 Q2 Q3 ENABLE T LOAD
CLOCK
2
15
RESET LOAD COUNT ENABLES ENABLE P ENABLE T
1 9 7 10 Clock PIN 16 = VCC PIN 8 = GND
GND
FUNCTION TABLE
Inputs Reset* L H H H H Load X L H H H Enable P X X H L X Enable T X X H X L Output Q Reset Load Preset Data Count No Count No Count
*HC163A only. HC161A is an Asynchronous Reset Device H = high level, L = low level, X = don't care
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 8
Publication Order Number: MC74HC161A/D
MC74HC161A, MC74HC163A
III II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
VCC Vin SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit V V V - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Plastic DIP SOIC Package mW Tstg TL - 65 to + 150 260
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
IIII I I I I IIIIIIIIIIIIIIIIIIIII II IIII II IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 0 0 0 + 125 1000 600 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
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2
II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
VOH
VOL
ICC
VIH
VIL
Iin
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND Iout = 0 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
MC74HC161A, MC74HC163A
v
v
v
v
Test Conditions
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3
v 3.6 mA v 4.0 mA v 5.2 mA v 3.6 mA v 4.0 mA v 5.2 mA
VCC V
6.0 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0
- 55 to 25_C
0.1 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.26 0.26 0.26 2.48 3.98 5.48 0.1 0.1 0.1 1.9 4.4 5.9
4.0
Guaranteed Limit
v 85_C v 125_C
1.0 0.33 0.33 0.33 2.34 3.84 5.34 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.1 0.1 0.1 1.9 4.4 5.9
40
1.0 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.4 0.4 0.4 0.1 0.1 0.1 2.2 3.7 5.2 1.9 4.4 5.9
160
Unit
A A V V V V
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II I I I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II II I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II II I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II II I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I III I I I I I I II I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol tTLH, tTHL tPHL tPHL tPLH tPHL tPLH tPHL tPHL tPLH fmax Cin Maximum Input Capacitance Maximum Output Transition Time, Any Output Maximum Propagation Delay, Reset to Ripple Carry Out (HC161A Only) Maximum Propagation Delay, Clock to Ripple Carry Out Maximum Propagation Delay, Enable T to Ripple Carry Out Maximum Propagation Delay, Reset to Q (HC161A Only) Maximum Propagation Delay, Clock to Q Maximum Clock Frequency (50% Duty Cycle)* Parameter
*Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However, if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable. See Applications information in this data sheet. NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Gate)*
MC74HC161A, MC74HC163A
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Fig. 1, 7 2, 7 2, 7 1, 7 1, 7 3, 7 3, 7 2, 7 1, 7 1, 7 1, 7 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- - 55 to 25_C Typical @ 25C, VCC = 5.0 V 155 120 22 18 145 100 22 20 120 75 22 18 135 100 18 15 145 100 20 17 145 100 22 18 120 75 20 16 110 60 16 14 6 15 30 35 10 75 30 15 13 Guaranteed Limit
4
v 85_C v 125_C
190 140 26 22
185 135 28 24
160 135 27 22
175 130 20 16
150 115 18 15
185 135 22 19
185 135 25 20
160 120 23 20
5 12 24 28
10
95 40 19 16
45 230 155 30 25 220 150 35 28 200 150 30 25 210 160 22 20 190 140 20 17 220 150 25 21 220 150 30 23 200 150 28 22 110 55 22 19 4 10 20 24 10
MHz
Unit
pF
pF ns ns ns ns ns ns ns ns ns
III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II II I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II II I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II II I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I III I I I I I I II I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol tr, tf trec trec tsu tsu tsu tsu tw tw th th th Maximum Input Rise and Fall Times Minimum Pulse Width, Reset (HC161A Only) Minimum Pulse Width, Clock Minimum Recovery Time, Load Inactive to Clock Minimum Recovery Time, Reset Inactive to Clock (HC161A Only) Minimum Hold Time, Clock to Enable T or Enable P Minimum Hold Time, Clock to Reset (HC163A Only) Minimum Hold Time, Clock to Load or Preset Data Inputs Minimum Setup Time, Enable T or Enable P to Clock Minimum Setup Time, Reset to Clock (HC163A Only) Minimum Setup Time, Load to Clock Minimum Setup Time, Preset Data Inputs to Clock Parameter
MC74HC161A, MC74HC163A
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Fig. 2 1 5 2 6 4 5 6 4 5 5 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 800 500 400 60 25 12 10 60 25 12 10 80 35 15 12 80 35 15 12 80 35 20 17 60 25 20 17 60 25 15 12 40 20 15 12 3 3 3 3 3 3 3 3 3 3 3 3 Guaranteed Limit
5
v 85_C v 125_C
1000 800 500 400 75 30 15 13 75 30 15 13 95 40 20 17 95 40 20 17 95 40 25 23 75 30 25 23 75 30 20 18 60 30 20 18 3 3 3 3 3 3 3 3 3 3 3 3
1000 800 500 400 110 50 26 23 110 50 26 23 110 50 35 25 90 40 18 15 90 40 18 15 90 40 35 25 90 40 30 20 80 40 30 20 3 3 3 3 3 3 3 3 3 3 3 3
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
MC74HC161A, MC74HC163A
FUNCTION DESCRIPTION The HC161A/163A are programmable 4-bit synchronous counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading and count-enable controls. The HC161A and HC163A are binary counters with asynchronous Reset and synchronous Reset, respectively.
INPUTS Clock (Pin 2)
level. The HC161A resets asynchronously, and the HC163A resets with the rising edge of the Clock input (synchronous reset).
Loading
The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting and loading occur with the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
With the rising edge of the Clock, a low level on Load (Pin 9) loads the data from the Preset Data input pins (P0, P1, P2, P3) into the internal flip-flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low.
Count Enable/Disable
These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip-flops and appear at the counter outputs. P0 (Pin 3) is the least-significant bit and P3 (Pin 6) is the most-significant bit.
OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These devices have two count-enable control pins: Enable P (Pin 7) and Enable T (Pin 10). The devices count when these two pins and the Load pin are high. The logic equation is:
Count Enable = Enable P * Enable T * Load
The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count-enable control: Enable T is both a count-enable and a Ripple-Carry Output control.
Table 1. Count Enable/Disable
Control Inputs Load H L X X Enable P H H L X Enable T H H H L Result at Outputs Q0 - Q3 Count No Count No Count No Count High when Q0-Q3 are maximum* High when Q0-Q3 are maximum* L Ripple Carry Out
These are the counter outputs. Q0 (Pin 14) is the least-significant bit and Q3 (Pin 11) is the most-significant bit.
Ripple Carry Out (Pin 15)
When the counter is in its maximum state 1111, this output goes high, providing an external look-ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is:
Ripple Carry Out = Enable T * Q0 * Q1 * Q2 * Q3 CONTROL FUNCTIONS Resetting
*Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.
A low level on the Reset pin (Pin 1) resets the internal flip-flops and sets the outputs (Q0 through Q3) to a low OUTPUT STATE DIAGRAMS
0 1 2 3 4
15
5
14
6
13
7
12
11
10
9
8
Binary Counters
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MC74HC161A, MC74HC163A
SWITCHING WAVEFORMS
tr 90% 50% 10% tw 1/fmax tPLH tPHL ANY OUTPUT 90% 50% 10% tTLH tTHL ANY OUTPUT tf VCC RESET GND tPHL 50% trec VCC CLOCK 50% GND 50% GND tw VCC
CLOCK
Figure 1.
Figure 2.
tr ENABLE T tPLH RIPPLE CARRY OUT tTLH 90% 50% 10% 90% 50% 10%
tf VCC GND tPHL CLOCK tTHL tsu 50% GND th VCC RESET 50%
Figure 3.
VALID INPUTS P0, P1, P2, P3 VCC 50% GND tsu LOAD 50% GND tsu CLOCK th 50% GND trec VCC CLOCK th VCC
Figure 4. HC163A Only
VALID ENABLE T OR ENABLE P VCC 50% GND tsu th VCC 50% GND
Figure 5. TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST CL*
Figure 6.
*Includes all probe and jig capacitance
Figure 7.
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7
P0
3
T0 R C C LOAD LOAD P0
Q0
14
Q0
Q0
P1 4
T1 R C C LOAD LOAD P1 T2 R C C LOAD LOAD P2
Q1
13
Q1
Figure 8. 4-Bit Binary Counter with Asynchronous Reset (MC74HC161A)
Q1
MC74HC161A, MC74HC163A
Q2
12
Q2
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P2
5
Q2
8
P3
6
T3 R C C LOAD LOAD P3
Q3
11
Q3
ENABLE P
7 VCC = PIN 16 GND = PIN 8 R LOAD LOAD 2 C C
15 RIPPLE CARRY OUT
ENABLE T RESET
10 1
LOAD CLOCK
9
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
MC74HC161A, MC74HC163A
Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one and two. 4. Inhibit. RESET (HC161A) RESET (HC163A) LOAD
(ASYNCHRONOUS) (SYNCHRONOUS)
P0 PRESET DATA INPUTS P1 P2 P3 CLOCK (HC161A) CLOCK (HC163A)
COUNT ENABLES
ENABLE P ENABLE T Q0 Q1
OUTPUTS Q2 Q3 RIPPLE CARRY OUT RESET
12 LOAD
13 14
15
0 COUNT
1
2 INHIBIT
Figure 9. Timing Diagram
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P0
3
T0 R C C LOAD LOAD P0
Q0
14
Q0
Q0
P1
4
T1 R C C LOAD LOAD P1 T2 R C C LOAD LOAD P2
Q1
13
Q1
Figure 10. 4-Bit Binary Counter with Synchronous Reset (MC74HC163A)
Q1
MC74HC161A, MC74HC163A
Q2
12
Q2
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P2
5
Q2
10
P3
6
T3 R C C LOAD LOAD P3
Q3
11
Q3
ENABLE P
7 VCC = PIN 16 GND = PIN 8 R LOAD LOAD
15 RIPPLE CARRY OUT
ENABLE T RESET
10 1
LOAD CLOCK
9 2
C C
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS CASCADING
LOAD INPUTS INPUTS INPUTS
LOAD H = COUNT L = DISABLE H = COUNT L = DISABLE
P0 P1 P2 P3
LOAD
P0 P1 P2 P3
LOAD
P0 P1 P2 P3
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT TO MORE SIGNIFICANT STAGES
RESET OUTPUTS CLOCK NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and Clock. OUTPUTS OUTPUTS
Figure 11. N-Bit Synchronous Counters
INPUTS LOAD ENABLE P ENABLE T LOAD P0 P1 P2 P3 LOAD
INPUTS
INPUTS
P0 P1 P2 P3
LOAD
P0 P1 P2 P3
ENABLE P ENABLE T CLOCK CLOCK R RESET Q0 Q1 Q2 Q3 RIPPLE CARRY OUT
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT
ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT TO MORE SIGNIFICANT STAGES
OUTPUTS
OUTPUTS
OUTPUTS
Figure 12. Nibble Ripple Counter
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MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HC163A
OTHER INPUTS Q0 Q1 Q2 Q3 RESET OPTIONAL BUFFER FOR NOISE REJECTION OUTPUT
HC163A
OTHER INPUTS Q0 Q1 Q2 Q3 RESET OPTIONAL BUFFER FOR NOISE REJECTION OUTPUT
Figure 13. Modulo-5 Counter
Figure 14. Modulo-11 Counter
The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous Reset.
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MC74HC161A, MC74HC163A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE R
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 10 0 10 0 0.020 0.040 1.01 0.51
B
1 8
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
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MC74HC161A, MC74HC163A
Notes
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MC74HC161A, MC74HC163A
Notes
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MC74HC161A, MC74HC163A
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MC74HC161A/D

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